Device having dual etch stop liner and reformed silicide layer and related methods

ABSTRACT

The present invention provides a semiconductor device having dual silicon nitride liners and a reformed silicide layer and related methods for the manufacture of such a device. The reformed silicide layer has a thickness and resistance substantially similar to a silicide layer not exposed to the formation of the dual silicon nitride liners. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to a silicide layer, removing a portion of the first silicon nitride liner, reforming a portion of the silicide layer removed during the removal step, and applying a second silicon nitride liner to the silicide layer.

BACKGROUND OF THE INVENTION

(1) Technical Field

The present invention relates generally to semiconductor devices andmore particularly to an NFET/PFET device having dual etch stop linersand silicide layers of normal thickness and resistance.

(2) Related Art

The application of stresses to field effect transistors (FETs) is knownto improve their performance. When applied in a longitudinal direction(i.e., in the direction of current flow), tensile stress is known toenhance electron mobility (or n-channel FET (NFET) drive currents) whilecompressive stress is known to enhance hole mobility (or p-channel FET(PFET) drive currents).

One way to apply such stresses to a FET is the use ofintrinsically-stressed barrier silicon nitride liners. For example, atensile-stressed silicon nitride liner may be used to cause tension inan NFET channel while a compressively-stressed silicon nitride liner maybe used to cause compression in a PFET channel. Accordingly, adual/hybrid liner scheme is necessary to induce the desired stresses inan adjacent NFET and PFET.

In the formation of a dual/hybrid barrier silicon nitride liners forstress enhancement of NFET/PFET devices, the first deposited liner mustbe removed in one of the two FET regions by patterning and etching. Forexample, FIG. 1 shows a typical device 100 comprising a buried silicondioxide (BOX) 110, a shallow trench isolation (STI) 120, an NFET 140, aspacer 142, a PFET 150, a spacer 152, and a suicide layer 130 a-d.Suicide layer 130 a-d may be any material known in the art, including,for example, cobalt silicide (CoSi₂), titanium silicide (TiSi₂),molybdenum silicide (MoSi₂), tungsten silicide (WSi₂), nickel silicide(Ni_(x)Si_(y)), and tantalum silicide (TaSi₂).

FIG. 2 shows the deposition of a first silicon nitride liner 160 ontodevice 100. In this case, first silicon nitride liner 160 is a tensilesilicon nitride, although other silicon nitrides may be used, including,for example, a compressive silicon nitride. In order to form adual/hybrid liner, a portion of first silicon nitride liner 160 must beremoved from one of the FET regions. In order to ensure sufficientcontact of a second deposited liner, it is preferable that first siliconnitride liner 160 be completely removed from the chosen FET region.However, complete removal of first silicon nitride liner 160 requires anoveretch, necessarily resulting in some etching of underlying silicidelayer 130 a-d.

Referring to FIG. 3, the masking of NFET 140 and etching of tensilesilicon nitride liner 160 adjacent PFET 150 results in an etchedsilicide layer 132 a-b adjacent PFET 150. Etching may be by any meansknown in the art, including, for example, anisotropic reactive ionetching (RIE).

In methods currently known in the art, a second silicon nitride liner isdeposited onto device 100 after etching, resulting in silicide layers ofdifferent thicknesses adjacent NFET 140 and PFET 150. In addition to adifference in thickness, etched silicide layer 132 a-b exhibitsincreased silicide resistance (R_(s)) relative to silicide layer 130a-b.

Silicide layer 130 a-b normally has a thickness between about 15 nm andabout 50 nm, with a corresponding R_(s) between about 6 ohm/sq and about20 ohm/sq. By comparison, etched silicide layer 132 a-b may have athickness between about 5 nm and about 40 nm, with a corresponding R_(s)between about 12 ohm/sq and about 40 ohm/sq.

Particularly in technologies beyond 90 nm, which utilize very ultrasmall gatelengths (e.g., <35 nm) and diffusion widths (e.g., <100 nm),such an increase in R_(s) is unacceptable for at least two reasons.First, the increases in R_(s) will impact performance of the device.Second, erosion of the silicide layer during the overetch increases thechance of failure by the polysilicon conductor (PC)-opens mechanism(i.e., the silicide on top of the PC is eroded or absent).

Accordingly, a need exists for a semiconductor device having dual etchstop liners and silicide layers of normal thickness and resistance andmethods for the manufacture of such a device.

SUMMARY OF THE INVENTION

The present invention provides a semiconductor device having dualsilicon nitride liners and a reformed silicide layer and related methodsfor the manufacture of such a device. The reformed silicide layer has athickness and resistance substantially similar to a silicide layer notexposed to the formation of the dual silicon nitride liners. A firstaspect of the invention provides a method for use in the manufacture ofa semiconductor device comprising the steps of applying a first siliconnitride liner to a silicide layer, removing a portion of the firstsilicon nitride liner, reforming a portion of the silicide layer removedduring the removal step, and applying a second silicon nitride liner tothe silicide layer.

A second aspect of the invention provides a method for use in themanufacture of a semiconductor device having an NFET and a PFET,comprising the steps of applying a first silicon nitride liner to theNFET, PFET, and a silicide layer adjacent at least one of the NFET andthe PFET, removing a portion of the first silicon nitride liner adjacentone of the NFET and the PFET, reforming a portion of the silicide layerremoved during the removal step, and applying a second silicon nitrideliner to the reformed silicide layer and the one of the NFET and thePFET.

A third aspect of the invention provides a method of reforming a portionof a silicide layer, comprising the steps of applying a metal layer to aremaining portion of an etched silicide layer, and forming a silicidewith the metal layer and the remaining portion of the silicide layer.

A fourth aspect of the invention provides a semiconductor device,comprising a first silicon nitride liner, a second silicon nitrideliner, and a partially reformed silicide layer, wherein a portion of thesilicide layer is formed by the resilicidation of a deposited metal.

The foregoing and other features of the invention will be apparent fromthe following more particular description of embodiments of theinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of this invention will be described in detail, withreference to the following figures, wherein like designations denotelike elements, and wherein:

FIG. 1 shows a prior art device including an NFET/PFET.

FIG. 2 shows deposition of a first silicon nitride liner to the priorart device of FIG. 1.

FIG. 3 shows damage to a silicide layer after etching the first siliconnitride liner from a portion of the prior art device of FIG. 2.

FIG. 4 shows deposition of a metal layer to the device of FIG. 3.

FIG. 5 shows a reformed silicide layer following silicidation of themetal layer in FIG. 4.

FIG. 6 shows deposition of a second silicon nitride liner to the deviceof FIG. 5.

FIG. 7 shows a finished device according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 4, after processing in a manner substantially the sameas that shown in the steps of FIGS. 1-3, a metal layer 265 is applied todevice 200. Metal layer 265 includes a metal present in themetal-silicon alloy of suicide layer 230 a-b, 232 a-b. For example,where silicide layer 230 a-b, 232 a-b is cobalt silicide (CoSi₂), metallayer 165 includes cobalt (Co).

In FIG. 5, a reformed silicide layer 234 a-b is formed on the surface ofetched silicide layer 232 a-b by a sintering process and anyunsilicidated metal layer is removed. Together, etched silicide layer232 a-b and reformed silicide layer 234 a-b make up resilicided layer235 a-b, having substantially the same thickness and resistance assilicide layer 230 a-b. Alternatively, resilicided layer 235 a-b may bethicker than silicide layer 230 a-b, with a corresponding decrease inR_(s). Thus, the device and methods of the present invention avoid boththe physical thinning of the silicide layer and the resulting increasein silicide resistance.

Referring now to FIG. 6, a compressive nitride liner 270 is applied todevice 200. Suitable silicon nitride liners may be formed by plasmaenhanced chemical vapor deposition (PECVD), rapid thermal chemical vapordeposition (RTCVD), or low pressure chemical vapor deposition (LPCVD).Formation by any of these methods is generally done at a temperaturebetween about 400° C. and about 750° C.

Finally, in FIG. 7, compressive silicon nitride liner 270 has beenmasked in an area adjacent PFET 250 and etched in an area adjacenttensile silicon nitride liner 260, forming the finished device 200 ofthe invention. Device 200 of FIG. 7 has a hybrid/dual etch stop liner260, 270 and a resilicided layer 235 a-b including etched silicide layer232 a-b and reformed silicide layer 234 a-b. Thus, device 200 provides ahybrid/dual etch stop liner 260, 270 without the increased silicideresistance associated with methods and devices known in the art.

While formation of device 200 has been described as involving thedeposition of a tensile silicon nitride liner 260 and the laterdeposition of a compressive silicon nitride liner 270, it should beappreciated that the order of deposition of these liners may bereversed. That is, it is also within the scope of the present inventionto form device 200 by the first deposition of a compressive siliconnitride liner 270, etching of compressive silicon nitride liner 270 froman area around NFET 240, resilicidation of etched silicide layer 232 a-b(this time adjacent NFET 240 rather than PFET 250), deposition of atensile silicon nitride liner 260, and patterning and etching of tensilesilicon nitride liner 260 from an area around PFET 250.

While this invention has been described in conjunction with the specificembodiments outlined above, it is evident that many alternatives,modifications and variations will be apparent to those skilled in theart. Accordingly, the embodiments of the invention as set forth aboveare intended to be illustrative, not limiting. Various changes may bemade without departing from the spirit and scope of the invention asdefined in the following claims.

1. A method for use in the manufacture of a semiconductor devicecomprising the steps of: applying a first silicon nitride liner to asilicide layer; removing a portion of the first silicon nitride liner;reforming a portion of the silicide layer removed during the removalstep; and applying a second silicon nitride liner to the silicide layer.2. The method of claim 1, further comprising the step of removing aportion of the second silicon nitride liner.
 3. The method of claim 1,wherein at least one of the first and second silicon nitride liners isformed by at least one of plasma enhanced chemical vapor deposition,rapid thermal chemical vapor deposition, and low pressure chemical vapordeposition.
 4. The method of claim 1, wherein the first silicon nitrideliner is a tensile silicon nitride liner.
 5. The method of claim 1,wherein the second silicon nitride liner is a compressive siliconnitride liner.
 6. The method of claim 1, wherein the reforming stepcomprises the steps of: applying a metal layer to the silicide layer;and forming a silicide with the metal layer and the silicide layer. 7.The method of claim 6, wherein the metal layer includes a metal presentin the silicide layer.
 8. The method of claim 7, wherein the metalincludes at least one of cobalt, titanium, molybdenum, tungsten,tantalum, nickel, and platinum.
 9. The method of claim 6, furthercomprising the step of removing a portion of the metal layer notincorporated into the silicide.
 10. The method of claim 1, wherein atleast one of a thickness and a resistance of the reformed silicide layeris substantially the same as before the removing step.
 11. The method ofclaim 1, wherein the reformed silicide layer is thicker than thesilicide layer before the removing step.
 12. A method for use in themanufacture of a semiconductor device having an NFET and a PFET,comprising the steps of: applying a first silicon nitride liner to theNFET, PFET, and a silicide layer adjacent at least one of the NFET andthe PFET; removing a portion of the first silicon nitride liner adjacentone of the NFET and the PFET; reforming a portion of the silicide layerremoved during the removal step; and applying a second silicon nitrideliner to the reformed silicide layer and the one of the NFET and thePFET.
 13. The method of claim 12, wherein the first silicon nitrideliner is a tensile silicon nitride liner and the second silicon nitrideliner is a compressive silicon nitride liner.
 14. The method of claim13, wherein the portion of the first silicon nitride liner removed isadjacent the PFET.
 15. The method of claim 12, wherein the applying ofat least one of the first silicon nitride liner and the second siliconnitride liner provides a stress to at least one of the NFET and thePFET.
 16. The method of claim 12, further comprising the step ofremoving a portion of the second silicon nitride liner from an areaadjacent the first silicon nitride liner.
 17. The method of claim 12,wherein the reforming step comprises the steps of: applying a metallayer to the silicide layer; and forming a silicide with the metal layerand the silicide layer.
 18. A method of reforming a portion of asilicide layer, comprising the steps of: applying a metal layer to aremaining portion of an etched silicide layer; and forming a silicidewith the metal layer and the remaining portion of the silicide layer.19. The method of claim 18, wherein the metal layer includes a metalpresent in the remaining portion of the etched silicide layer.
 20. Themethod of claim 19, wherein the metal includes at least one of cobalt,titanium, molybdenum, tungsten, tantalum, nickel, and platinum.
 21. Themethod of claim 18, further comprising the step of removing a portion ofthe metal layer not formed into the silicide.
 22. A semiconductordevice, comprising: a first silicon nitride liner; a second siliconnitride liner; and a partially reformed silicide layer, wherein aportion of the silicide layer includes a resilicided deposited metal.23. The device of claim 22, wherein at least one of the first and secondsilicon nitride liners is formed by at least one of plasma enhancedchemical vapor deposition, rapid thermal chemical vapor deposition, andlow pressure chemical vapor deposition.
 24. The device of claim 22,wherein the first silicon nitride liner is a tensile silicon nitrideliner.
 25. The device of claim 22, wherein the second silicon nitrideliner is a compressive silicon nitride liner.
 26. The device of claim22, wherein the first silicon nitride liner substantially covers a firstdevice and the second silicon nitride liner substantially covers asecond device.
 27. The device of claim 26, wherein the first device isan NFET and the second device is a PFET.
 28. The device of claim 27,wherein the first silicon nitride liner is a tensile silicon nitrideliner and the second silicon nitride liner is a compressive siliconnitride liner.
 29. The device of claim 28, wherein at least one of thefirst silicon nitride liner and the second silicon nitride linerprovides a stress to at least one of the NFET and the PFET.
 30. Thedevice of claim 29, wherein the stress improves at least one of electronmobility and hole mobility compared to an NFET and a PFET notsubstantially covered by a tensile silicon nitride liner and acompressive silicon nitride liner, respectively.